Efficient algorithms for 2D area management and online task placement on runtime reconfigurable FPGAs

Partial Runtime Reconfigurable (PRTR) FPGAs allow HW tasks to be placed and removed dynamically at runtime. We make two contributions in this paper. First, we present an efficient algorithm for finding the complete set of Maximal Empty Rectangles on a 2D PRTR FPGA. We also present a HW implementation of the algorithm with negligible runtime overhead. Second, we present an efficient online deadline-constrained task placement algorithm for minimizing area fragmentation on the FPGA by using an area fragmentation metric that takes into account probability distribution of sizes of future task arrivals as well as the time axis. The techniques presented in this paper are useful in an operating system for runtime recon-figurable FPGAs to manage the HW resources on the FPGA when HW tasks that arrive and finish dynamically at runtime. Reconfigurable HW devices such as Field Programmable Gate Arrays (FPGAs) are very popular in today's embedded systems design due to their low-cost, high-performance and flexibility. A FPGA consists of a rectangular grid of Configurable Logic Blocks (CLBs), also referred to as cells, and the interconnects between them. FPGAs are inherently parallel, that is, two or more HW tasks can execute on a FPGA concurrently as long as they can both fit on it. Partial Runtime Reconfigurable (PRTR) FPGAs, such as the Virtex family of FPGAs from Xilinx, allow part of the FPGA area to be rec-onfigured while the remainder continues to operate without interruption. In other words, HW tasks can be placed and removed dynamically at runtime. A FPGA can be 1D reconfigurable, where each task occupies a contiguous set of columns, or 2D reconfigura-ble, where each task occupies a rectangular area. Early versions of Xilinx FPGA devices, such as Virtex-II and Spartan, only support 1D reconfiguration. In 2006, Xilinx introduced the Early-Access Partial Reconfiguration Flow (EAPR) to permit 2D reconfiguration. Virtex-4 and Virtex-V devices support independent reconfiguration of a minimum of 16 CLBs in the same column, making it possible to have 2D dynamic reconfiguration [1]. In this paper, we address the problem of online scheduling of soft real-time HW tasks with unknown arrival times and execution times on a 2D PRTR FPGA. Certain tasks may be rejected when the system is overloaded. The goal is to minimize task rejection ratio while guaranteeing all accepted tasks to meet their deadlines. We first introduce some notations. The FPGA reconfigurable area contains W Â H cells forming a rectangle of …